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vishay siliconix dg9414, dg9415 document number: 71766 s11-0984-rev. g, 23-may-11 www.vishay.com 1 this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 single 4 x 1 and dual 2 x 1 multiplexers features ? low voltage operation (+ 2.7 v to + 12 v) ? low on-resistance - r ds (on): 14 ? ? low power consumption ? ttl compatible ? esd protection > 2000 v (method 3015.7) ? available in tsso p-10 (aka msop-10) ? compliant to rohs directive 2002/95/ec benefits ? high accuracy ? simple logic interface ? reduce board space applications ? battery operated systems ? portable test equipment ? sample and hold circuits ? cellular phones ? communication systems ? networking equipment description the dg9414, a single 4 to 1 multiplexer, and the dg9415, a dual 2 x 1 multiplexer, are monolithic cmos analog devices designed for high performance low voltage operation. combining low power, high speed, low on-resistance and small physical size, the dg9414 and dg9415 are ideal for portable and battery powered applications requiring high performance and efficient use of board space. both the dg9414 and dg9415 are built on vishay siliconix?s low voltage bcd-15 process. minimum esd protection, per method 3015.7, is 2000 v. an epitaxial layer prevents latchup. break-before-make is guaranteed for dg9415. functional block diagram and pin configuration x = do not care x = do not care en a 1 a 0 on switch 1 x x none 00 0 no 0 00 1 no 1 01 0 no 2 01 1 no 3 no 2 v+ no 3 dg9414dq com no 1 no 0 en a 0 1 2 3 4 10 9 8 7 gnd a 1 56 logic en a 0 on switch 1 x none 00 nc 1 nc 2 01 no 1 no 2 no 1 v+ com 1 dg9415dq com 2 nc 1 no 2 en nc 2 1 2 3 4 10 9 8 7 gnd a 0 56 logic ordering information temp range package part number - 40 c to 85 c msop-10 dg9414dq-t1-e3 dg9415dq-t1-e3
www.vishay.com 2 document number: 71766 s11-0984-rev. g, 23-may-11 vishay siliconix dg9414, dg9415 this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 notes: a. signals on s x , d x or in x exceeding v+ or v- will be clamped by internal diodes. limit forward diode current to maximum current ratings. b. all leads soldered or welded to pc board. absolute maximum ratings parameter limit unit reference v+ to gnd - 0.3 to + 13 v in, com, nc, no a - 0.3 to (v+ + 0.3) continuous current (any terminal) 20 ma peak current (pulsed at 1 ms, 10 % duty cycle) 40 esd (method 3015.7) > 2000 v storage temperature (d suffix) - 65 to 150 c specifications (v+ = 3 v) parameter symbol test conditions otherwise unless specified v+ = 3 v, 10 % , v in = 0.4 v or 2.4 v e temp. a limits - 40 c to 85 c unit min. c typ. b max. c analog switch analog signal range d v analog full 0 v+ v on-resistance r on v+ = 2.7 v, v com = 1 v/1.5 v/2 v i no or i nc = 5 ma room full 63 97 101 ? r on match d ? r on room 3 11 r on flatness d,f r on flatness room 14 33 no or nc off leakage current g i no/nc(off) v+ = 3.3 , v no or v nc = 0.3 v/3 v v com = 3 v/0.3 v room full - 1 - 10 1 10 na com off leakage current g i com(off) room full - 1 - 10 1 10 channel-on leakage current g i com(on) v+ = 3.3 v v com = v no or v nc = 0.3 v/3 v room full - 1 - 10 1 10 digital control input current g i inl or i inh v in = 0 or v+ full - 1 1 a input high voltage d v inh full 1.6 v input low voltage d v inl full 0.4 dynamic characteristics tu r n - o n t i m e t on v no or v nc = 1.5 v room full 102 125 142 ns turn-off time t off room full 45 68 75 break-before-make time t d room 7 78 transition time t trans v no = 1.5 v/0 v, v nc = 0 v/1.5 v room full 81 128 144 charge injection d q inj c l = 1 nf, v gen = 0 v, r gen = 0 ? room 3 pc off-isolation oirr r l = 50 ? , c l = 5 pf, f = 1 mhz room - 58 db channel-to-channel crosstalk (dg9415) x ta l k r l = 50 ? , f = 1 mhz room - 64 no, nc off capacitance c no(off) , c nc(off) f = 1 mhz dg9414 room 11 pf dg9415 room 10 com off capacitance c com(off) dg9414 room 26 dg9415 room 13 com on capacitance c com(on) dg9414 room 43 dg9415 room 25 power supply power supply range v+ 2.7 3.3 v power supply current h i+ v+ = 3.3 v, v in = 0 v or 3.3 v full 1 a
document number: 71766 s11-0984-rev. g, 23-may-11 www.vishay.com 3 vishay siliconix dg9414, dg9415 this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 notes: a. room = 25 c, full = as determined by the operating suffix. b. typical values are for design aid only, not guaranteed nor subject to production testing. c. the algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this datas heet. d. guarantee by design, nor subjected to production test. e. v in = input voltage to perform proper function. f. difference of min and max values. g. guaranteed by 12 v leakage testing, not production tested. h. guaranteed by worst case test conditions and not subject to test. specifications (v+ = 5 v) parameter symbol test conditions otherwise unless specified v+ = 5 v, 10 % , v in = 0.8 v or 2.4 v e temp. a limits - 40 c to 85 c unit min. c typ. b max. c analog switch analog signal range d v analog full 0 v+ v on-resistance r on v+ = 4.5 v, v com = 1.5 v/2.5 v/3.5 v i no or i nc = 10 ma room full 33 56 60 ? r on match ? r on room 2 10 r on flatness f r on flatness room 10 20 no or nc off leakage current g i no/nc(off) v+ = 5.5 v, v no or v nc = 1 v/4.5 v v com = 4.5 v/1 v room full - 1 - 10 1 10 na com off leakage current g i com(off) room full - 1 - 10 1 10 channel-on leakage current g i com(on) v+ = 5.5 v v com = v no or v nc = 1 v/4.5 v room full - 1 - 10 1 10 digital control input current h i inl or i inh v in = 0 or v+ full - 1 1 a input high voltage d v inh full 1.8 v input low voltage d v inl full 0.6 dynamic characteristics tu r n - o n t i m e h t on v no or v nc = 3 v room full 56 77 86 ns turn-off time h t off room full 25 46 50 break-before-make timet h t d room 7 34 transition time t trans v no = 3 v/ 0 v, v nc = 0 v/3 v room full 47 77 84 off-isolation oirr r l = 50 ? , c l = 5 pf, f = 1 mhz room - 58 db channel-to-channel crosstalk (dg9415) x ta l k r l = 50 ? , f = 1 mhz room - 64 charge injection d q inj c l = 1 nf, v gen = 0 v, r gen = 0 ? room 6 pc no, nc off capacitance c no(off) , c nc(off) f = 1 mhz dg9414 room 11 pf dg9415 room 10 com off capacitance c com(off) dg9414 room 25 dg9415 room 13 com on capacitance c com(on) dg9414 room 42 dg9415 room 24 power supply power supply range v+ 4.5 5.5 v power supply current h i+ v+ = 5.5 v, v in = 0 v or 5.5 v full 1 a
www.vishay.com 4 document number: 71766 s11-0984-rev. g, 23-may-11 vishay siliconix dg9414, dg9415 this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 notes: a. room = 25 c, full = as determined by the operating suffix. b. typical values are for design aid only, not guaranteed nor subject to production testing. c. the algebraic convention whereby the most negative value is a minimum and the most po sitive a maximum, is used in this datas heet. d. guarantee by design, nor s ubjected to production test. e. v in = input voltage to perform proper function. f. difference of min and max values. g. guaranteed by 12 v leakage te sting, not production tested. h. guaranteed by worst case test conditions and not subject to test. stresses beyond those listed under ?absolute maximum ratings? ma y cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other condit ions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. specifications (v+ = 12 v) parameter symbol test conditions unless specified v+ = 12 v, v in = 0.8 v or 2.4 v e temp. a limits - 40 c to 85 c unit min. c typ. b max. c analog switch analog signal range d v analog full 0 12 v r on match ? r on room 1 9 ? r on flatness d,f r on flatness room 1 10 on-resistance r on v+ = 10.8 v, i no , i nc = 25 ma v com = 2/9 v room full 14 17 19 switch off leakage current i no(off) i nc(off) v com = 1/11 v v no , v nc = 11/1 v room full - 1 - 10 1 10 na i com(off) room full - 1 - 10 1 10 channel on leakage current i com(on) v no , v nc = v com = 11/1 v room full - 1 - 10 1 10 digital control input current i inl or i inh v in = 0 or v+ full - 1 1 a input high voltage d v inh full 2.4 v input low voltage d v inl full 0.8 dynamic characteristics tu r n - o n t i m e h t on r l = 300 ? , c l = 35 pf v no , v nc = 5 v see figure 2 room full 33 55 59 ns turn-off time h t off room full 17 40 41 break-before-make time delay h t d dg419l only, v nc , v no = 5 v r l = 300 ? , c l = 35 pf room 2 24 transition time t trans v no = 5 v/ 0 v, v nc = 0 v/ 5 v room full 29 56 59 charge injection d q inj v g = 0 v, r g = 0 ? , c l = 1 nf room 13 pc off isolation d oirr r l = 50 ? , c l = 5 pf f = 1 mhz room - 58 db channel-to-channel crosstalk d x ta l k room - 64 no, nc off capacitance d c no(off) , c nc(off) v in = 0 or v+, f = 1 mhz dg9414 room 10 pf dg9415 room 10 com off capacitance c com(off) dg9414 room 24 dg9415 room 13 com on capacitance d c com(on) dg9414 room 40 dg9415 room 23 power supplies positive supply current i+ v in = 0 v or 12 v full 1 a
document number: 71766 s11-0984-rev. g, 23-may-11 www.vishay.com 5 vishay siliconix dg9414, dg9415 this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 typical characteristics (25 c, unless otherwise noted) r on vs. v com and supply voltage supply current vs. temperature leakage current vs. temperature 0 10 20 30 40 50 60 70 80 0369 v+ = 3.0 v i s = 5 ma v com - analog voltage (v) - on-resistance ( ? ) r on v+ = 5.0 v i s = 10 ma v+ = 12.0 v i s = 25 ma t = 25 c 12 1 10 100 1000 10000 - 60 - 40 - 20 0 20 40 60 80 100 temperature ( c) supply current (na) i+ - v+ = 5.0 v v+ = 12.0 v v ax , v en = 0 v temperature ( c) leakage current (pa) 1 10 100 1000 - 60 - 40 - 20 0 20 40 60 80 100 i com(off) v+ = 12 v i com(on) i no(off) , i nc(off) r on vs. analog voltage and temperature supply current vs. input switching frequency leakage vs. analog voltage 0 10 20 30 40 50 60 70 80 024681012 a = 85 c b = 25 c c = - 40 c - on-resistance ( ? ) r on v com - analog voltage (v) a c a b c v+ = 3.0 v i s = 5 ma a b c b v+ = 5.0 v i s = 10 ma v+ = 12.0 v i s = 25 ma input switching frequency (hz) 10 100 1 k 10 k 100 k 1 m 10 m 1 n 10 n 100 n 1 m 10 m 1 10 100 supply current (na) i+ - v+ = 12 v -100 - 60 - 20 20 60 100 02468 v com , v no , v nc - analog voltage (v) i com(on) leakage current (pa) v+ = 12.0 v i no(off) /i nc(off) i com(off) 10 12
www.vishay.com 6 document number: 71766 s11-0984-rev. g, 23-may-11 vishay siliconix dg9414, dg9415 this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 typical characteristics (25 c, unless otherwise noted) transistion time vs. temperature (dg9414) switching time vs. temperature insertion loss, off-isolation crosstalk vs. frequency (dg9415) 0 20 40 60 80 100 120 - 60 - 40 - 20 0 20 40 60 80 100 t trans- v+ = 3 v temperature ( c) t trans+ v+ = 3 v t trans - v+ = 5 v t trans+ v+ = 5 v t trans+ v+ = 12 v t trans - v+ = 12 v - switching time (ns) 0 20 40 60 80 100 120 140 - 60 - 40 - 20 0 20 40 60 80 100 t on v+ = 3 v t on , t off temperature ( c) t on v+ = 5 v t on v+ = 12 v t off v+ = 3 v t off v+ = 5 v t off v+ = 12 v talk 100 k 1 m - 30 10 - 70 - 50 100 m 1 g frequency (hz) - 90 oirr loss 10 m - 10 loss, oirr, x (db) v+ = 12 v r l x ta l k transistion time vs. temperature (dg9415) insertion loss, off-isolation crosstalk vs. frequency (dg9414) switching threshold vs. supply voltage 0 20 40 60 80 100 120 - 60 - 40 - 20 0 20 40 60 80 100 t trans- v+ = 3 v temperature ( c) t trans+ v+ = 3 v t trans- v+ = 5 v t trans+ v+ = 5 v t trans+ v+ = 12 v t trans- v+ = 12 v talk 100 k 1 m - 30 10 - 70 - 50 100 m 1 g frequency (hz) - 90 oirr loss 10 m - 10 loss, oirr, x (db) v+ = 12 v r l x talk 0.0 0.5 1.0 1.5 2.0 2.5 3.0 - switching threshold (v) v+ - supply voltage (v) v t 2 4 6 8 10 12 14
document number: 71766 s11-0984-rev. g, 23-may-11 www.vishay.com 7 vishay siliconix dg9414, dg9415 this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 typical characteristics (25 c, unless otherwise noted) schematic diagram (typical channel) test circuits charge injection vs. analog voltage (dg9414) -50 -30 -10 10 30 50 v com - analog voltage (v) q - charge injection (pc) v+ = 3 v v+ = 5 v v+ = 12 v 0 2 4 6 8 10 12 charge injection vs. analog voltage (dg9415) - 50 - 30 - 10 10 30 50 v com - analog voltage (v) q - charge injection (pc) v+ = 3 v v+ = 5 v v+ = 12 v 0 2 4 6 8 10 12 1 level shift/ drive v in s v+ gnd d v- v+ figure 2. switching time logic input switch output 50 % 0 v t r < 5 ns t f < 5 ns 90 % t off t on v out note: logic input waveform is inverted for switches that have the opposite logic sense control c l (includes fixture and stray capacitance) v+ in r l r l + r on v out = v in no or nc com v out gnd c l 35 pf r l 300 ? v+ v in switch input switch output v inh v inl 0.9 x v out
www.vishay.com 8 document number: 71766 s11-0984-rev. g, 23-may-11 vishay siliconix dg9414, dg9415 this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 test circuits figure 3. break-before-make c l (includes fixture and stray capacitance) nc v no no v nc 0 v logic input switch output v o v nc = v no t r < 5 ns t f < 5 ns 90 % t d t d in com v+ gnd v+ c l 35 pf v o r l 300 ? v inh v inl figure 4. transition time c l (includes fixture and stray capacitance) r l r l + r on v o = v s v+ in c l 35 pf r l 300 ? v o v s2 v s1 gnd +15 v 50 % logic input switch output v s1 t r < 5 ns t f < 5 ns 10 % t trans+ 90 % v 01 v s2 v 02 t trans- no or nc com nc or no v inh v inl figure 5. charge injection c l 1 nf r g v o v+ com in v g gnd off on off v o ? v o in in dependent on switch configuration input polarity determined by sense of switch. v+ v in = 0 - v+ q = ? v o x c l no or nc
document number: 71766 s11-0984-rev. g, 23-may-11 www.vishay.com 9 vishay siliconix dg9414, dg9415 this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 test circuits vishay siliconix maintains worldwide manufacturing capability. pr oducts may be manufactured at one of several qualified locatio ns. reliability data for silicon technology and package reliability represent a composite of all qualified locations. for related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?71766 . figure 6. crosstalk no or nc x talk isolation = 20 log v out v in c = rf bypass com v s 0 v or 2.4 v in 50 ? r g = 50 ? v+ gnd c v+ v in nc or no v out figure 7. off isolation r l 50 ? com 0 v, 2.4 v v+ r g = 50 ? gnd off isolation = 20 log v com v no/nc in no or nc c c = rf bypass figure 8. source/drain capacitances no or nc in com v+ gnd 0 v, 2.4 v meter hp4192a impedance analyzer or equivalent c v+ f = 1 mhz
notes: 1. die thickness allowable is 0.203 0.0127. 2. dimensioning and tolerances per ansi.y14.5m-1994. 3. dimensions ?d? and ?e 1 ? do not include mold flash or protrusions, and are measured at datum plane -h- , mold flash or protrusions shall not exceed 0.15 mm per side. 4. dimension is the length of terminal for soldering to a substrate. 5. terminal positions are shown for reference only. 6. formed leads shall be planar with respect to one another within 0.10 mm at seating plane. 7. the lead width dimension does not include dambar protrusion. allowable dambar protrusion shall be 0.08 mm total in excess of the lead width dimension at maximum material condition. dambar cannot be located on the lower radius or the lead foot. minimum space between protrusions and an adjacent lead to be 0.14 mm. see detail ?b? and section ?c-c?. 8. section ?c-c? to be determined at 0.10 mm to 0.25 mm from the lead tip. 9. controlling dimension: millimeters. 10. this part is compliant with jedec registration mo-187, variation aa and ba. 11. datums -a- and -b- to be determined datum plane -h- . 12. exposed pad area in bottom side is the same as teh leadframe pad size. 5 n n-1 a b c 0.20 (n/2) tips) 2x n/2 2 1 0.60 0.50 0.60 e top view e see detail ?b? -h- 3 d -a- seating plane a 1 a 6 c 0.10 side view 0.25 bsc 4 l -c- seating plane 0.07 r. min 2 places parting line detail ?a? (scale: 30/1) 0.48 max detail ?b? (scale: 30/1) dambar protrusion 7 c 0.08 m b s a s b b 1 with plating base metal c 1 c section ?c-c? scale: 100/1 (see note 8) see detail ?a? a 2 0.05 s c c ? 3 e 1 -b- end view e1 0.95 package information vishay siliconix document number: 71245 12-jul-02 www.vishay.com 1 msop: 10?leads jedec part number: mo-187, (variation aa and ba) n = 10l millimeters dim min nom max note a - - 1.10 a 1 0.05 0.10 0.15 a 2 0.75 0.85 0.95 b 0.17 - 0.27 8 b 1 0.17 0.20 0.23 8 c 0.13 - 0.23 c 1 0.13 0.15 0.18 d 3.00 bsc 3 e 4.90 bsc e 1 2.90 3.00 3.10 3 e 0.50 bsc e 1 2.00 bsc l 0.40 0.55 0.70 4 n 10 5 0 4 6 ecn: t-02080?rev. c, 15-jul-02 dwg: 5867
document number: 91 000 www.vishay.com revision: 11-mar-11 1 disclaimer legal disclaimer notice vishay all product, product specifications and data ar e subject to change without notice to improve reliability, function or design or otherwise. vishay intertechnology, inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectivel y, vishay), disclaim any and all liability fo r any errors, inaccuracies or incompleteness contained in any datasheet or in any o ther disclosure relating to any product. vishay makes no warranty, representation or guarantee regarding the suitability of the products for any particular purpose or the continuing production of any product. to the maximum extent permitted by applicab le law, vishay disc laims (i) any and all liability arising out of the application or use of any product, (ii) any and all liability, incl uding without limitation specia l, consequential or incidental dama ges, and (iii) any and all impl ied warranties, including warran ties of fitness for particular purpose, non-infringement and merchantability. statements regarding the suitability of pro ducts for certain types of applications are based on vishays knowledge of typical requirements that are often placed on vishay products in gene ric applications. such statements are not binding statements about the suitability of products for a partic ular application. it is the customers responsibility to validate that a particu lar product with the properties described in th e product specification is su itable for use in a particul ar application. parameters provided in datasheets an d/or specifications may vary in different applications and perfo rmance may vary over time. all operating parameters, including typical pa rameters, must be validated for each customer application by the customers technical experts. product specifications do not expand or otherwise modify vishays term s and conditions of purchase, including but not limited to the warranty expressed therein. except as expressly indicated in writing, vishay products are not designed for use in medical, life-saving, or life-sustaining applications or for any other application in which the failure of the vishay product co uld result in person al injury or death. customers using or selling vishay products not expressly indicated for use in such applications do so at their own risk and agr ee to fully indemnify and hold vishay and it s distributors harmless from and against an y and all claims, liabilities, expenses and damages arising or resulting in connection with such use or sale, including attorneys fees, even if such claim alleges that vis hay or its distributor was negligent regarding the design or manufact ure of the part. please contact authorized vishay personnel t o obtain written terms and conditions regarding products designed fo r such applications. no license, express or implied, by estoppel or otherwise, to any intelle ctual property rights is gran ted by this document or by any conduct of vishay. product names and markings noted herein may be trademarks of their respective owners.

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